1. Field of the Invention
The present invention generally relates to program execution systems for executing a program stored in a memory and, more particularly, to a program execution system for efficiently duplicating a program function code in a fast memory so that the code is executed by a CPU.
2. Description of the Related Art
In general, the speed at which a program is executed by a program execution system such as a computer system is largely affected by the data transfer rate between a processing unit (CPU) and a memory for storing the program (program memory). For instance, when the data transfer rate is low, a high arithmetic capability of the CPU cannot be fully exploited. In general, a fast memory with a high data transfer rate may be more expensive than a normal memory and the memory capacity installable in the system may be small.
Thus, in the related art, the program execution rate is increased by building in a fast memory in a computer system to improve the data transfer rate between the CPU and the program memory. The fast memory is used in combination with the normal memory for storing the program so that the performance of the fast memory is taken advantage of.
The related art technology with the above-described feature is demonstrated in a system as shown in FIG. 40 which includes a cache memory as a fast memory. FIG. 40 is a block diagram showing the related-art computer system. Referring to FIG. 40, numeral 1001 indicates a CPU, 1002 indicates a cache memory and 1003 indicates a normal memory. The term "normal memory" refers to a memory with an operating speed slower than that of the cache memory 1002 and a memory size larger than that of the cache memory 1002.
In the related-art computer system shown in FIG. 40, the cache memory 1002 implementing the fast memory is placed between the normal memory 1003 which stores the program and the CPU 1001. The cache memory 1002 is used as a location to temporarily store duplicated program codes stored in the normal memory 1003.
Whenever the normal memory 1003 is accessed by the CPU 1001 to execute the program stored in the normal memory 1003, a check is made to determine whether a duplicate of the program code to be accessed is located in the cache memory 1002, that is, whether the code is duplicated in the cache memory 1002.
When the duplicate of the program code to be accessed is located in the cache memory 1002, the duplicate is used. When the program code cannot be located, the program code to be accessed is read from the normal memory 1003, whereupon it is duplicated in the cache memory 1002 and then executed.
When not all of the program codes accessed by the CPU 1001 can be stored in the cache memory 1002, the CPU 1001 removes program codes from the cache memory 1002 and stores duplicates of new program codes in the cache memory 1002.
One aspect of the related-art concerning the cache memory 1002 is that it is necessary to effect a high-speed determination as to whether the duplicate of the program code to be accessed is located in the cache memory 1002. Since this determination is made every time the CPU 1001 accesses the normal memory 1003, that is, for each instruction which the CPU 1001 executes, this determination should be made at a sufficiently high speed to make the duration of determination negligible relative to the instruction execution rate of the CPU 1001. A distinctive feature of the cache memory 1002 implementing the fast memory lies in its high access speed. Therefore, if the speed of determination is slow, the benefit of the cache memory 1002 is not available even if the program codes are read from the cache memory 1002 at a high speed.
In the related-art program execution system with the above-described construction, not only a determination operation but also all of the operations related to the cache memory 1002 are controlled using hardware. For this reason, the related-art computer system with the cache memory 1002 built in may be complicated. That is, the hardware circuitry and the control of the cache memory 1002 tend to be complicated.
Another thing of note is that, while the cache memory 1002 implementing the fast memory provides a benefit of high-speed operation, it poses problems such as expensiveness and limitation in the memory capacity. Thus, duplicating all program codes from the normal memory 1003 to the cache memory 1002 is impossible. For this reason, the controllers for the CPU 1001 and the cache memory 1002 control duplication in the cache memory 1002 by exercising appropriate determination in accordance with the flow of process.